1. Field of the Invention
The present invention relates to a non-volatile semiconductor device, and more particularly, to a configuration for ensuring security to maintain the confidentiality of stored information.
2. Description of the Background Art
Non-volatile semiconductor memory devices such as a flash EEPROM (Electrically Erasable/Programmable Read Only Memory; hereinafter referred to as xe2x80x9cflash memoryxe2x80x9d) have advantageous characteristics that data can be stored in a non-volatile manner and can be held without any power supply.
FIG. 18 schematically shows the entire configuration of a conventional flash memory. In FIG. 18, a flash memory 900 includes: a memory array 901 having a plurality of non-volatile memory cells arranged in a matrix of rows and columns; an X-decoder 902 for selecting a row of memory cells in memory array 901 in accordance with a received X-address; a Y-decoder 903 for generating a column selecting signal for selecting a column of memory cells in memory array 901; a Y-gate 904 for connecting a selected column of memory array 901 to an internal data line in accordance with the column selecting signal received from Y-decoder 903; and a data register 905 for temporarily storing write data in data writing. Data register 905 includes a register circuit provided corresponding to each of the columns of memory cells in memory array 901, and stores write data applied via Y-gate 904. Writing and write verification of data are carried out in accordance with the data stored in data register 905.
Flash memory 900 further includes: a data input/output buffer 907 for externally inputting/outputting data via a data/address terminal group 906; an address input buffer 908 for receiving an address signal applied via address/data terminal group 906 to generate internal address signals (X- and Y-address signals); and a control signal input buffer circuit 910 receiving control signals applied via a control terminal group 909 to generate internal control signals.
The control signals applied to control terminal group 909 include an output enable signal OE instructing reading of data, a chip enable signal CE instructing that flash memory 900 is selected, and a write enable signal WE designating data writing or the timing of command taking.
Control signal input buffer circuit 910 includes an OE buffer 910a receiving output enable signal OE, a CE buffer 910b receiving chip enable signal CE, a WE buffer 910c receiving write enable signal WE, and a buffer 910d receiving the other control signals. When chip enable signal CE is activated, flash memory 900 determines that the externally-applied control signals are valid and takes in currently applied data/address signal. An internal output enable signal from OE buffer 910a is applied to data input/output buffer 907 and to address input buffer 908, and an internal chip enable signal from CE buffer 910b is also applied to data input/output buffer 907 and address input buffer 908. When both output enable signal OE and chip enable signal CE are activated, data reading is carried out.
Flash memory 900 further includes: an X-address buffer 911 for buffering the internal address signal received from address input buffer 908 to generate an internal X-address signal to be supplied to X-decoder 902; a write data input driver 912 buffering the write data received from data input/output buffer 907 and writing the data into data register 905 via Y-gate 904 in data writing; a read data output amplifier 913 for amplifying internal read data read out via Y-gate 904 and applying the amplified data to data input/output buffer 907 in data reading; a command control circuit 914 receiving the internal control signals from control signal input circuit 910 and the command from address input buffer 908 and determining a designated operation mode; a read/write/erasure control circuit 915 generating control signals required for the designated operation mode according to the operation mode instruction from command control circuit 914; and a high voltage generating circuit 916 for generating a high voltage required for the write/erasure, under the control of read/write/erasure control circuit 915.
For example, when the internal chip enable signal from CE buffer 910b is being activated, command control circuit 914 takes in a command from address input buffer 908 in response to the rise of the internal write enable signal from WE buffer 910c and decodes the command that is taken in. Read/write/erasure control circuit 915 is constituted by a processor such as a sequence controller, and generates control signals required for the operation designated by command control circuit 914 to control the operation of each circuit.
High voltage generating circuit 916 generates a high voltage to be required for write/erasure. The high voltage generated by high voltage generating circuit 916 is different depending on a configuration of the memory array, and portions that require such a voltage are supplied with the generated high voltage. To the memory cells and the substrate region, a high voltage is actually applied via X-decoder 902, Y-decoder 904 and a source line decoder (not shown). Though FIG. 18 shows that the high voltage from high voltage generating circuit 916 is applied to X-decoder 902, the high voltage generated by high voltage generating circuit 916 may also be applied to the substrate region of memory array 901 (on a sector basis) or to a source line.
Read/write/erasure control circuit 915 further controls command control circuit 914 for the acceptance of a command in writing/erasing. Read/write/erasure control circuit 915 controls the operation of X-address buffer 911 to sequentially change an X-address in erasure verification mode and to select memory cells when a flash (collective) erasure is performed at the erasing operation, for example.
In memory array 901, each of the non-volatile memory cells arranged in a matrix of rows and columns is generally constituted by a floating gate type transistor, and stores information depending on a threshold voltage of the floating gate type transistor.
FIG. 19 shows an example of a configuration of memory array 901 shown in FIG. 18. FIG. 19 exemplifies a configuration of an array portion of an AND-type flash memory.
In FIG. 19, memory cells MC are arranged in rows and columns, and an arrangement example is shown in FIG. 19, in which memory cells are arranged in 10 rows and 5 columns. A memory cell MC is constituted by one floating gate type field effect transistor MT. A bit line BL (BL1-BL5) is arranged corresponding to each column of memory cells MC, and a word line WL (WL1-WL10) is arranged corresponding to each row of memory cells MC. These memory cells MC are divided into a plurality of sectors in the column direction. One sector is constituted by memory units MU each including a predetermined number (five in FIG. 19) of memory cells MC in each column. The memory cells MC included in the same memory unit MU are connected in parallel between a sub bit line SBL and a sub source line SSL. Sub bit line SBL is connected to a corresponding bit line BL (BL1-BL5) via a drain-side sector selecting transistor SWD, whereas sub source line SSL is connected to a main source line MSL via a source-side sector selecting transistor SWS. Drain-side sector selecting transistor SWD is selectively rendered conductive in response to a sector selecting signal VD (VD1, VD2), whereas source-side sector selecting transistor SWS is selectively rendered conductive in response to a sector selecting signal VS (VS1, VS2). In the AND-type flash memory, data can be erased sector by sector, and hence fast re-writing of data can be realized.
A memory cell MC stores information depending on the threshold voltage of memory transistor MT.
FIG. 20 shows an example of the distribution of the threshold voltages of memory cells MC. In FIG. 20, the vertical axis indicates the voltage and the horizontal axis indicates the distribution (the relative number of memory cells). In FIG. 20, when a memory cell has a threshold voltage included in a region of xe2x80x9c1,xe2x80x9d the memory cell is in an erased state, whereas when a memory cell has a threshold voltage included in a region of xe2x80x9c0,xe2x80x9d the memory cell is in a written state (programmed state). This means that the memory cell in the erased state stores data xe2x80x9c1,xe2x80x9d and the memory cell in the written or programmed state stores data xe2x80x9c0.xe2x80x9d
Application of a voltage VWL1 between the threshold voltage in the written state and that in the erased state to the control gates of memory transistors MT (to a word line) renders memory cells MC conductive or non-conductive in accordance with the stored information therein. This is detected by read data output amplifier 913 shown in FIG. 18, and thus data reading is performed.
Specifically, for example, when data stored in a memory cell connected to a word line WL3 is read out, a source voltage VL1 on main source line MSL provided corresponding to a sector including word line WL3 is set to a ground voltage (0V), and sector selecting signals VD1 and VS1 are set to the voltage level of e.g. 7V. Sector selecting signals VD2 and VS2 are at the level of the ground voltage. The high voltage of e.g. 7V is applied to sector selecting signals VD1 and VS1 so that sector selecting transistors SWD and SWS attain a deep ON state and that data in the memory cells can rapidly and reliably be read out. A read voltage VWL1 is applied to word line WL3, and a non-selecting voltage VWL4 is applied to the remaining word lines WL1, WL2, WL4 and WL5. Read voltage VWL1 is at an intermediate voltage level that lies between the upper limit of the threshold voltage in the erased state and the lower limit of the threshold voltage in the written state. When the threshold voltages of memory cell MC connected to word line WL 3 is in the region of xe2x80x9c1,xe2x80x9d memory transistor MT is rendered conductive, and a corresponding bit line BL (any one of BL1 to BL5) will be electrically connected to main source line MSL by sector selecting transistors SWD and SWS and the selected memory transistor MT, or the corresponding bit line BL is short-circuited to the ground voltage.
Whereas, when the threshold voltage of memory transistor MT is in the region of xe2x80x9c0xe2x80x9d in FIG. 20, the corresponding memory transistor MT is non-conductive, and a corresponding bit line BL is isolated from source lines SSL and MSL.
In memory cell MC supplied with non-selecting voltage VWL4 at control gates thereof, the threshold voltage is higher than non-selecting voltage VWL4, irrespective of the region where the threshold voltages lies, i.e. irrespective of whether the memory cell is in the region xe2x80x9c1xe2x80x9d or in the region xe2x80x9c0,xe2x80x9d and the memory cell MC is maintained non-conductive. Therefore, the memory cells connected to these non-selected word lines have no effects on reading of the data in memory cells MC connected to selecting word line WL3.
In such a state, whether or not current flows in a corresponding bit line BL, or whether or not bit line BL is maintained in a pre-charged state is detected by read data output amplifier 913, and data reading is performed in accordance with the result of the detection.
The threshold voltage is set in accordance with stored information by injecting/extracting electrons into/from the floating gate.
FIG. 21 schematically shows a configuration of a memory transistor MT constituting a memory cell MC. In FIG. 21, memory transistor MT includes: impurity regions 921 and 922 formed spaced from each other on the surface of a substrate region 920; a floating gate 923 formed on a channel region between impurity regions 921 and 922 with a gate insulating film (not shown) interposed; and a control gate 924 formed on floating gate 923 with an interlayer insulating film (not shown) interposed. Floating gate 923 is enclosed by the insulating film to be electrically insulated, so that the state of storing electrons in floating gate 923 does not change even at the power-off, allowing non-volatile storage of information.
Injection/extraction of electrons into/from floating gate 923 is carried out by utilizing channel hot electrons or by utilizing Fowler-Nordheim (FN) tunneling current. FIG. 21 shows an applied voltage when electrons e are injected into floating gate 923 using the FN tunneling current. In the injection of electrons, a positive high voltage of e.g. 15V is applied to control gate 924, and substrate region 920 and impurity regions 921 and 922 are set to the ground voltage (0V). This allows the FN tunneling current to flow between floating gate 923 and substrate region 920 or impurity regions 921 and 922, and thus electrons are injected into floating gate 923. In a state where electrons are injected into floating gate 923, memory transistor MT has a high threshold voltage, and thus the memory cell is in a written state where data xe2x80x9c0xe2x80x9d is stored therein.
FIG. 22 shows an applied voltage to the memory transistor when electrons are extracted from the floating gate. When the electrons e are extracted from the floating gate, a negative high voltage of e.g. xe2x88x9216V is applied to the control gate, and a positive voltage of e.g. 2V is applied to impurity regions 921 and 922 and substrate region 920. In this state, the FN tunneling current flow is caused to allow the electrons to flow from floating gate 923 to substrate region 920 or to impurity regions 921 and 922, and thus the electrons are extracted from floating gate 923. In such a state where the electrons are extracted, memory transistor MT has a reduced threshold voltage.
Which of the written state (programmed state) and the erased state of a memory cell corresponds to which of the state with a high threshold voltage (hereinafter referred to as xe2x80x9chigh-threshold statexe2x80x9d) and a state with a low threshold voltage hereinafter referred to as xe2x80x9clow-threshold statexe2x80x9d) is determined depending on an array configuration and a control method. That is, in one flash memory, the high-threshold state is associated with the erased state whereas the low-threshold state is associated with the written state. However, in either case, a complicated procedure is required for the two states of the memory cell to fall within the threshold-voltage distribution regions specific to the respective states. A procedure of the erasing operation used where the low-threshold state is correlated with the erased state, as shown in FIG. 20, will be described below.
FIG. 23 is a flow chart representing the procedure of the erasing operation. First, an erasure address specifying an erasure region and an erasure command are supplied (step S1). When the erasure is performed sector by sector, a sector address is applied specifying a sector for which the erasure is to be performed. When the erasure command is applied, read/write/erasure control circuit 915 shown in FIG. 18 generates a voltage required for the erasing operation, i.e. a negative high voltage (xe2x88x9216V) and a positive voltage (2V) (step 2). The negative high voltage is generated by a high voltage generating circuit 916 shown in FIG. 18. Subsequently, an erasing bias is applied to the target memory cells for erasure, under the control of read/write/erasure control circuit 916 (step S3). In application of the erasing bias, in the array configuration shown in FIG. 18, sector selecting signals VD and VS are driven to be in a selected state in accordance with an address signal, and a negative high voltage is applied to a word line WL via the X-decoder. Source voltage VS on main source line MSL is set to be at 2V, and a voltage of 2V is transmitted to a bit line BL. The application of the erasing bias to the memory cells is performed in a pulse-like manner, and is stopped after a predetermined time period.
Subsequently, an erasure verification voltage VWL2 to be transmitted onto word line WL is generated in order to determine whether or not the memory cells are in the erased state (step S4). Thereafter, a row and a column are selected, and the erasure verification voltage VWL2 is transmitted onto a selected word line (step S5).
Erasure verification voltage VWL2 corresponds to the upper limit of the threshold voltage in the erasure state, as shown in FIG. 24. In this state, it is determined whether or not the memory cells are conductive and the threshold voltages thereof are distributed within the region of xe2x80x9c1xe2x80x9d shown in FIG. 24 (step S6). If a memory cell is non-conductive in the determining operation, meaning that the memory cell is not yet in the erasure state, the number of applications of the erasing bias is increased by one, and the erasing bias is re-applied (step S7). Subsequently, it is determined whether or not the number of times of application of the erasing bias exceeds a predetermined limit number of times (step S8). If it exceeds the limit number, it is considered as occurrence of an erasure failure, and a necessary error process is carried out (step S9).
If the number of times of application of the erasing bias is no more than the limit number, the procedure from step S3 et seq. is executed again.
Erasure verification is carried out in step S6, and if the threshold voltages are distributed within the region xe2x80x9c1xe2x80x9d and if it is determined that all the target memory cells for erasing are in the erasure state, then the voltage transmitted to the word line is set to be at an over-erasure verification voltage VWL3 in order to determine whether or not these memory cells are in an excessively erased state (over-erasure state) (step S10). The over-erasure verification voltage VWL3 corresponds to a voltage of the lower limit in the distribution of the threshold voltages within the region of xe2x80x9c1xe2x80x9d The erasure verifying operation is again carried out by transmitting over-erasure verification voltage VWL3 onto a word line of a erasure target via the X-decoder (step 11). Subsequently, it is determined whether or not current flows in bit line, as in the case of the erasure verification. All the memory cells of a erasure target are checked for over-erasure. If all the target memory cells are maintained non-conductive at the application of over-erasure verification voltage VWL3, it is determined that the erasing is normally performed (step S12). If the result of the check for the over-erasing indicates successful, a process required for terminating the erasing operation is executed (step S13). The terminating process in the step S13 includes, for example, a process of resetting the erasure voltage in step S12.
If current flows in the bit line in step S12, it indicates that an over-erased memory cell is present, and the threshold voltage of the memory cell in the over-erasure state must be increased back to be within the region of xe2x80x9c1xe2x80x9d, and hence a write-back procedure is executed as described below.
FIG. 25 is a flow chart showing the write-back procedure. The write-back procedure shown in FIG. 25 is also executed under the control of read/write/erasure control circuit 915 shown in FIG. 18. First, in order to apply a voltage required for the write-back, a required high voltage is generated by high voltage generating circuit 916 under the control of read/write/erasure control circuit 915 (step S20). At the write-back, a positive high voltage (15V) is applied to the control gate of a target memory cell for write-back, and the ground voltage (0V) is applied to the source (source line) and the drain (bit line). The write-back process is executed for the memory cell in the over-erasure state.
Subsequent to the step S20 of setting up the power-supply, a row and a column are selected, and a write-back bias is applied to the memory cell in the over-erasure state (step S21). The write-back bias is also applied in the pulse-like manner and is applied only for a predetermined time period. Subsequently, in order to verify whether or not the write-back is normally executed, the potential of the word line to which the target memory cell for the write-back is connected is set to the voltage level of over-erasure verification voltage VWL3 (step S22). In this state, whether or not current flows in the bit line is detected (step S23).
Subsequently, in step S24, it is determined whether or not current flows in the bit line. If the current flows in the bit line, the memory cell is still in the over-erasure state, so that the number of times of application of the write-back bias is incremented by one (step S25). Then, it is determined whether or not the number of times of application of the write-back bias exceeds the limit number of times (step S26), and if it does not exceed the limit number, the processes from step S20 et seq. is executed again. On the other hand, if the number of times of application of the write-back bias exceeds the limit, it means that the memory cell is in the over-erasure state, and the memory cell is determined as a failure and a necessary error process is executed (step S27).
On the other hand, if it is determined, in step in S24, that no current flows in the bit line and the write-back is normally performed, the voltage of the word line of the target memory cell for the write-back is set to an over-write (over-programming) verification voltage VWL2 in order to determine whether or not the threshold voltage of the memory cell is beyond the distribution region of the threshold voltages in the erasure state due to this write-back (step S28). The over-write verification voltage VWL2 is at a voltage level corresponding to the threshold voltage of the upper limit in the distribution of the threshold voltages in the region of xe2x80x9c1xe2x80x9d in FIG. 24. Subsequently, a column is selected, and data in an internal memory cell is read out to detect whether or not current flows in the bit line (step S29). In step S29, if all the target memory cells for the write-back are conductive, meaning that the write-back is normally performed, then a necessary process for termination of the write-back is executed (step S31). By step S31, one erasing operation is completed. In step S30, if an over-written memory cell is present in the target memory cells for the write-back, it is determined that the normal erasing could not be carried out, and the error process in step S27 is executed.
A series of such process procedures allows the distribution of threshold voltages of the memory cells in the erasure state to fall within the region of xe2x80x9c1.xe2x80x9d
It is noted that, in a flash memory in which the high-threshold state is defined as the erasure state, erasing is carried out by the procedure of increasing the threshold voltage whereas writing or programming is carried out by the procedure of reducing the threshold voltage in the above-described process procedures shown in FIGS. 23 and 25. The process procedures shown in FIGS. 23 and 25 can be used only by replacing the terms xe2x80x9cerasure/writexe2x80x9d with each other. Therefore, in such a flash memory, a process similar to the process procedure shown in FIGS. 23 and 25 can be executed in programming.
A flash memory requires no power-supply for holding of data, so that it is suitable for the purpose of data storage in portable equipment and so forth. However, when personal information or the like is stored, which requires confidentiality, a mechanism for protecting (concealing) such data in some form is necessary to prevent the storage information from leaking to an outside. Though the flash memory generally contains a configuration utilizing a lock bit for inhibiting rewriting of information or a configuration utilizing a write protect program, such a configuration only inhibits rewriting of data, and reading out of information is not inhibited.
When a circuit-wise solution is provided within a memory as a mechanism for securing such confidentiality, the chip area is increased, leading to an increased cost. Moreover, when a protection circuit for securing the confidentiality is provided external to the flash memory, the circuit scale of the entire system is increased, also leading to the increased cost. Furthermore, an external circuit may possibly be disassembled, causing a problem in that the protection mechanism is decoded and no longer functions as the mechanism for maintaining confidentiality.
An object of the present invention is to provide a flash memory that can easily maintain the confidentiality of stored data without increase of a circuit scale.
Another object of the present invention is to provide a flash memory including a lock mechanism for maintaining the confidentiality of stored data, and an unlock function of reconstructing the stored data concealed by the lock mechanism data, with only a minimum necessary addition/change in a part of a control sequence.
A non-volatile semiconductor memory device according to the present invention includes a memory array having a plurality of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a plurality of bit lines, each of which is arranged corresponding to each of the columns; and a plurality of word lines, each of which is arranged corresponding to each of the rows. The non-volatile memory cell is constituted by a memory transistor having different threshold voltages in accordance with stored information.
The non-volatile semiconductor memory device according to the present invention further includes a circuit for reading data in accordance with whether or not a selected bit line is connected to a predetermined voltage source via corresponding memory cell in data reading; and a control circuit for setting a state of at least one row of memory cells to a first state affecting data reading of the other rows of memory cells in accordance with a first operation mode instruction.
In the first operation mode, the state of at least one row of memory cells is set to be in the first state affecting the data reading of the other rows of memory cells, so that data in the other rows of memory cells cannot be normally read in the first operation mode, and hence the other rows of memory cells can be concealed from the outside.
The state of the memory cells can be set simply by changing the level of erasure/write verification voltage. Therefore, there is no need to add a dedicated circuit and an existing write/erasure control sequence can be utilized, resulting in minimum necessary increase of the control sequence.
Furthermore, by allowing a second state, the memory cells set at the first state can be set in a state not affecting data reading of the other rows of memory cells, so that data stored in the other rows of memory cells can be read out, and thus an unlock mechanism can similarly be realized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.